Design of Low Power Write Driver Circuit for 10t Sram Cell
نویسندگان
چکیده
Aggressive scaling of transistor dimensions with each technology generation has resulted an increased integration density and improved device performance at the expense of increased leakage current. Diagnosis is becoming a major concern with the rapid development of semiconductor memories. In this paper, we propose a very low cost Design-forDiagnosis (DfD) solution for design of write driver circuit and to improve access time in write operation, in which two decoders and one sense amplifier are used in each column of 10T Static Random Access Memory (SRAM) cell. In SRAM bitcells utilizing minimum sized transistors are susceptible to various random process variations. The 10T SRAM cell for low voltage and energy constrain application is analyzed with respect to power dissipation. The analyzed 10T SRAM cell is compared with low power 6T SRAM cell. The simulation result based on 32nm technology shows that 37.03% power reduction compared to 6T SRAM bit cell. A control circuitry is used to enable the both column decoder and row decoder. However, there is a marginal increment in the area due to additional components used in the proposed design without compromising with the power.
منابع مشابه
New Low-Power and High-Speed 9T SRAM cell in Dynamic Domino Logic
This study presents the design of low power 9T SRAM cell using dynamic domino logic to achieve low power dissipation. The internal structure of the proposed 9T SRAM has cross coupled dynamic inverters which periodically updates the internal node voltage levels which, increase the read and write stability of the circuit. The SRAM design also has charge keeper transistor which resolves the proble...
متن کاملUltra Low-Power Fault-Tolerant SRAM Design in 90nm CMOS Technology
.................................................................................................................................. iii TABLE OF CONTENTS ............................................................................................................... iv LIST OF FIGURES ....................................................................................................................
متن کاملDesign of a Low Power 10T SRAM Cell
SRAM is a semiconductor memory cell. In this paper, a 10T SRAM cell is designed by using cadence virtuoso tool in 180nm CMOS technology. Its performance characteristics such as power, delay, and power delay product are analysed. 10T SRAM cell is basically 6T SRAM cell with 4 extra transistors. In this 10T SRAM cell, additional read circuitry is attached to avoid flipping of cell. The power diss...
متن کاملA Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability
This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...
متن کاملA Survey of Design Low Power Static Random Access Memory
In this field research paper explores the design and analysis of Static Random Access memories (SRAMs) that focuses on optimizing delay and power. CMOS SRAM cell consumes very less power and have less read and write time. Higher cell ratios will decrease the read and write time and improve stability. PMOS semiconductor unit with fewer dimensions reduces the ability consumption. During this pape...
متن کامل